Mikroprozessor AMD K6-III+

Kern:

Sharptooth

Low-Power Unterstützung:

Clock Control
   - Halt State
   - Stop Grant State
   - Stop Grant Inquire State
   - Enhanced stop grant state
   - Stop Clock State
System Management Mode

Architektur:

Advanced 6-Issue RISC86 Superscalar K6 Microarchitecture
   - Ten parallel specialized execution units
   - Multiple sophisticated x86-to-RISC86 instruction decoders
   - Advanced two-level branch prediction
   - Speculative execution
   - Out-of-order execution
   - Register renaming and data forwarding
   - Issues up to six RISC86 instructions per clock
Level1 Cache - 2-way set associative
                   - separater Befehlscache zzgl. 20-Kbytes predecode cache
                   - separater dual-ported write-back Datencache
                   - MESI protocol support
Level2 Cache - 4-way set-associative
                    - gemeinsamer write-back Befehls- und Datencache
Multiport internal cache design enabling simultaneous 64-bit reads/writes of Level1 and Level2 caches